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19-1838; Rev 3; 3/04
P Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset
General Description
The MAX6323/MAX6324 microprocessor (P) supervisory circuits monitor power supplies and P activity in digital systems. A watchdog timer looks for activity outside an expected window of operation. Six lasertrimmed reset thresholds are available with 2.5% accuracy from +2.32V to +4.63V. Valid RESET output is guaranteed down to VCC = +1.2V. The RESET output is either push-pull (MAX6323) or open-drain (MAX6324). RESET is asserted low when VCC falls below the reset threshold, or when the manual reset input (MR) is asserted low. RESET remains asserted for at least 100ms after VCC rises above the reset threshold and MR is deasserted. The watchdog pulse output (WDPO) utilizes an opendrain configuration. It can be triggered either by a fast timeout fault (watchdog input pulses are too close to each other) or a slow timeout fault (no watchdog input pulse is observed within the timeout period). The watchdog timeout is measured from the last falling edge of watchdog input (WDI) with a minimum pulse width of 300ns. WDPO is asserted for 1ms when a fault is observed. Eight laser-trimmed timeout periods are available. The MAX6323/MAX6324 are offered in a 6-pin SOT23 package and operate over the extended temperature range (-40C to +125C). Min/Max (Windowed) Watchdog, 8 Factory-Trimmed Timing Options Pulsed Open-Drain, Active-Low Watchdog Output Power-On Reset Precision Monitoring of +2.5V, +3.0V, +3.3V, and +5.0V Power Supplies Open-Drain or Push-Pull RESET Outputs Low-Power Operation (23A typ) Debounced Manual Reset Input Guaranteed Reset Valid to VCC = +1.2V
Features
MAX6323/MAX6324
Ordering Information
PART* TEMP RANGE PINPACKAGE RESET OUTPUT
Applications
Automotive Industrial Medical Embedded Control Systems
MAX6323_UT__-T -40C to +125C 6 SOT23-6 Push-Pull MAX6324_UT__-T -40C to +125C 6 SOT23-6 Open Drain *These devices are factory trimmed to one of eight watchdogtimeout windows and one of six reset voltage thresholds. Insert the letter corresponding to the desired watchdog-timeout window (A, B, C, D, E, F, G, or H) into the blank following the number 6323 or 6324 (see Watchdog Timeout table). Insert the two-digit code (46, 44, 31, 29, 26, or 23) after the letters UT for the desired nominal reset threshold (see Reset Threshold Range table at end of data sheet). Note: There are eight standard versions of each device available (see Standard Versions table). Sample stock is generally held on standard versions only. Standard versions have an order increment requirement of 2500 pieces. Nonstandard versions have an order increment requirement of 10,000 pieces. Contact factory for availability of nonstandard versions.
Pin Configuration
TOP VIEW
MR 1 6 RESET
Watchdog Timeout
SUFFIX A B C D E F G H WATCHDOG TIMEOUT* FAST SLOW MAX MIN UNITS UNITS 1.5 ms 10 15 ms 100 ms 15 ms 300 15 ms 10 s 15 ms 60 23 ms 47 ms 39 ms 82 719 ms 1.3 s
GND 2
MAX6323 MAX6324
5
WDPO
WDI 3
4
VCC
SOT23 Typical Operating Circuit appears at end of data sheet.
*See Figure 1 for operation. 1
________________________________________________________________ Maxim Integrated Products
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P Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323/MAX6324
ABSOLUTE MAXIMUM RATINGS
Terminal Voltage (with respect to GND) VCC ..................................................................-0.3V to +6.0V MR, RESET (MAX6323), WDI .............-0.3V to (VCC + +0.3V) WDPO, RESET (MAX6324) ..............................-0.3V to +6.0V Input Current, VCC, WDI, MR ..............................................20mA Output Current, RESET, WDPO ..........................................20mA Rate of Rise, VCC ............................................................100V/s Continuous Power Dissipation (TA = +70C) 6-Pin SOT23 (derate 8.7mW/C above +70C) ..........696mW Operating Temperature Range .........................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = full range, TA = -40C to +125C, unless otherwise noted. Typical values are at VCC = 3V, TA = +25C.) (Note 1) PARAMETER Operating Voltage Range Supply Current SYMBOL VCC ICC No load, RESET deasserted MAX632_ _UT46 MAX632_ _UT44 Reset Threshold Voltage VTH MAX632_ _UT31 MAX632_ _UT29 MAX632_ _UT26 MAX632_ _UT23 Reset Timeout Delay VCC to RESET Delay tRP RESET deasserted 10mV/ms, VTH +100mV to VTH -100mV ISINK = 1.2mA, VCC = 2.25V (MAX632_ _UT23, MAX632_ _UT26, MAX632_ _UT29, MAX632_ _UT31) WDPO, RESET Output Voltage VOL ISINK = 3.2mA, VCC = 4.25V (MAX632_ _UT44, MAX632_ _UT46) ISINK = 100A, VCC > 1.2V, RESET asserted ISOURCE = 500A, VCC = 3.15V, RESET deasserted (MAX632_ _UT23, MAX632_ _UT26, 0.8 x VCC MAX632_ _UT29, MAX632_ _UT31) ISOURCE = 800A, VCC = 4.75V, RESET V - 1.5 deasserted, (MAX632_ _UT44, MAX632_ _UT46) CC ILKG V RESET = V WDPO = +5.5V, RESET, WDPO deasserted 1 A VCC = 2.5V or 3.3V VCC = 5.5V 4.50 4.25 3.00 2.85 2.55 2.25 100 CONDITIONS MIN 1.2 23 27 4.63 4.38 3.08 2.93 2.63 2.32 180 20 0.4 V 0.4 0.4 TYP MAX 5.5 45 57 4.75 4.50 3.15 3.00 2.70 2.38 280 ms s V UNITS V A
RESET Output Voltage (MAX6323)
VOH
V
WDPO, RESET Output Leakage
2
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P Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset
ELECTRICAL CHARACTERISTICS (continued)
(VCC = full range, TA = -40C to +125C, unless otherwise noted. Typical values are at VCC = 3V, TA = +25C.) (Note 1) PARAMETER SYMBOL CONDITIONS MAX632_AUT_ _ MAX632_BUT_ _ MAX632_CUT_ _ Watchdog Timeout (Fast) (Notes 2, 3) tWD1 MAX632_DUT_ _ MAX632_EUT_ _ MAX632_FUT_ _ MAX632_GUT_ _ MAX632_HUT_ _ MAX632_AUT_ _ MAX632_BUT_ _ MAX632_CUT_ _ Watchdog Timeout (Slow) (Note 4) tWD2 MAX632_DUT_ _ MAX632_EUT_ _ MAX632_FUT_ _ MAX632_GUT_ _ MAX632_HUT_ _ Minimum Watchdog Input Pulse Width WDI Glitch Immunity WDI Input Voltage WDI Input Current WDPO Pulse Width MANUAL RESET INPUT MR Input Voltage MR Minimum Pulse Width MR Glitch Immunity MR to Reset Delay MR Pullup Resistance VCC = 2.5V VCC = 2.5V 50 VIH VIL 1 100 120 85 0.7 x VCC 0.3 x VCC V s ns ns k VIH VIL WDI = 0 WDI = VCC VIL = 0.8V, VIH = 0.75V x VCC 0.5 -1.5 -1 1 1 1.5 3 VCC = 5.5V 0.75 x VCC 0.8 MIN 1 10 10 10 10 17 29 543 10 100 300 10 60 47 82 1.3 300 100 TYP MAX 1.5 15 15 15 15 23 39 719 15 150 450 15 90 63 108 1.8 s ms s ns ns V A ms ms ms UNITS WATCHDOG INPUT AND OUTPUT
MAX6323/MAX6324
3
Note 1: Devices are tested at TA = +25C and guaranteed by design for TA = TMIN to TMAX, as specified. Note 2: WDPO will pulse low if a falling edge is detected on WDI before this timeout period expires. Note 3: To avoid a potential fake fault, the first WDI pulse after the rising edge of RESET or WDPO will not create a fast watchdog timeout fault. Note 4: WDPO will pulse low if no falling edge is detected on WDI after this timeout period expires.
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P Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323/MAX6324
Typical Operating Characteristics
(VCC = full range, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
MAX6323/24-01
POWER-DOWN RESET DELAY vs. TEMPERATURE
MAX6323/24-02
MR TO RESET DELAY vs. TEMPERATURE
140 MR TO RESET DELAY (ns) 120 100 80 60 40 20 0
MAX6323/24-03
40 35 SUPPLY CURRENT (A) 30 25 20 15 10 5 0 -40 -20 0 20 40 60 80 TEMPERATURE (C) VCC = 1.0V VCC = 3.3V VCC = 5.5V
30 POWER-DOWN RESET DELAY (s) 25 20 15 10 5 0 -40 -20 0 20 40 60 80 TEMPERATURE (C) VOD = 20mV
160
VOD = 100mV
-40
-20
0
20
40
60
80
TEMPERATURE (C)
NORMALIZED RESET THRESHOLD vs. TEMPERATURE
MAX6323/24-04
NORMALIZED POWER-UP RESET TIMEOUT vs. TEMPERATURE
NORMALIZED WATCHDOG TIMEOUT PERIOD (FAST)
MAX6323/24-05
NORMALIZED WATCHDOG TIMEOUT PERIOD (FAST) vs. TEMPERATURE
1.006 1.004 1.002 1.000 0.998 0.996 0.994 0.992 -40 -20 0 20 40 60 80 TEMPERATURE (C)
MAX6323/24-06
1.0005 1.0000 RESET THRESHOLD
1.008 1.006 POWER-UP RESET TIMEOUT 1.004 1.002 1.000 0.998 0.996
1.008
0.9995
0.9990
0.9985
0.9980 -40 -20 0 20 40 60 80 TEMPERATURE (C)
0.994 -40 -20 0 20 40 60 80 TEMPERATURE (C)
NORMALIZED WATCHDOG OUTPUT PULSE WIDTH (s)
NORMALIZED WATCHDOG TIMEOUT PERIOD (SLOW) vs. TEMPERATURE
NORMALIZED WATCHDOG TIMEOUT PERIOD (SLOW)
MAX6323/24-07
NORMALIZED WATCHDOG OUTPUT PULSE WIDTH vs. TEMPERATURE
MAX6323/24-08
MAXIMUM TRANSIENT DURATION vs. RESET THRESHOLD OVERDRIVE
VOD = VTH - VCC MAXIMUM TRANSIENT DURATION (s) 350 300 250 200 150 100 50 0 1 10 MAX632_AUT23 100 1000 RESET ASSERTED ABOVE THIS LINE
MAX6323/24-09
1.003 1.002 1.001 1.000 0.999 0.998 0.997 0.996 0.995 -40 -20 0 20 40 60 80 TEMPERATURE (C)
1.008 1.006 1.004 1.002 1.000 0.998 0.996 0.994 0.992 -40 -20 0 20 40 60 80 TEMPERATURE (C)
400
RESET COMPARATOR OVERDRIVE (mV)
4
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P Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset
Typical Operating Characteristics (continued)
(VCC = full range, TA = +25C, unless otherwise noted.)
SLOW WATCHDOG TIMEOUT PERIOD
MAX6323/24-11
MAX6323/MAX6324
FAST WATCHDOG TIMEOUT PERIOD
MAX6323/24-10
WDI
2V/div
WDI
2V/div
WDPO
2V/div
WDPO
2V/div
MAX6323AUT23 500s/div
MAX6323AUT23 5ms/div
Pin Description
PIN NAME FUNCTION Active-Low, Manual Reset Input. When MR is asserted low, RESET is asserted low, the internal watchdog timer is reset to zero, and WDPO is reset to high impedance (open drain). After the rising edge of MR, RESET is asserted for at least 100ms. Leave MR unconnected or connect to VCC if unused. Ground Watchdog Input. The internal watchdog timer clears to zero on the falling edge of WDI or when RESET goes high. If WDI sees another falling edge within the factory-trimmed watchdog window, WDPO will remain unasserted. Transitions outside this window, either faster or slower, will cause WDPO to pulse low for 1ms (typ). Supply Voltage for the Device. Input for VCC reset monitor. For noisy systems, bypass VCC with a 500pF (min) capacitor. Watchdog Pulse Output. The open-drain WDPO output is pulsed low for 1ms (typ) upon detection of a fast or slow watchdog fault. WDPO is only active when RESET is high. Active-Low. Reset is asserted when VCC drops below VTH and remains asserted until VCC rises above VTH for the duration of the reset timeout period. The MAX6323 has a push-pull output and the MAX6324 has an open-drain output. Connect a pullup resistor from RESET to any supply voltage up to +6V.
1
MR
2
GND
3
WDI
4
VCC WDPO
5
6
RESET
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5
P Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323/MAX6324
tWD1 (min) ) POSSIBLE STATES tWD1 (max) tWD2 (min) tWD2 (max)
GUARANTEED TO ASSERT WDPO
GUARANTEED NOT TO ASSERT WDPO
GUARANTEED TO ASSERT WDPO
*UNDETERMINED
*UNDETERMINED
CONDITION 1
FAST FAULT
CONDITION 2
NORMAL OPERATION
CONDITION 3
SLOW FAULT
*UNDETERMINED STATES MAY OR MAY NOT GENERATE A FAULT CONDITION.
Figure 1. Detailed Watchdog Input Timing Relationship
Detailed Description
The MAX6323/MAX6324 P supervisory circuits maintain system integrity by alerting the P to fault conditions. In addition to a standard V CC monitor (for power-on reset, brownout detect, and power-down reset), the devices include a sophisticated watchdog timer that detects when the processor is running outside an expected window of operation for a specific application. The watchdog signals a fault when the input pulses arrive too early (faster than the selected tWD1 timeout period) or too late (slower than the selected tWD2 timeout period) (Figure 1). Incorrect timing can lead to poor or dangerous system performance in tightly controlled operating environments. Incorrect timing could be the result of improper P clocking or code execution errors. If a timing error occurs, the MAX6323/MAX6324 issue a watchdog pulse output, independent from the reset output, indicating that system maintenance may be required.
other (faster than tWD1) (Figure 2) or falling edges that are too far apart (slower than tWD2) (Figure 3), WDPO is pulsed low. Normal watchdog operation is displayed in Figure 4 (WDPO is not asserted). The internal watchdog timer is cleared when a WDI falling edge is detected within the valid watchdog window or when the device's RESET or WDPO outputs are deasserted. All WDI input pulses are ignored while either RESET or WDPO is asserted. Figure 1 identifies the input timing regions where WDPO fault outputs will be observed with respect to tWD1 and tWD2. After RESET or WDPO deasserts, the first WDI falling edge is ignored for the fast fault condition (Figure 2). Upon detecting a watchdog fault, the WDPO output will pulse low for 1ms. WDPO is an open-drain output. Connect a pullup resistor on WDPO to any supply up to +6V.
VCC Reset
The MAX6323/MAX6324 also include a standard VCC reset monitor to ensure that the P is started in a known state and to prevent code execution errors during power-up, power-down, or brownout conditions. RESET is asserted whenever the VCC supply voltage
Watchdog Function
A pulse on the watchdog output WDPO can be triggered by a fast fault or a slow fault. If the watchdog input (WDI) has two falling edges too close to each
6
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P Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323/MAX6324
tWDI < tWD1 (min) RESET
WDI
WDPO
FAST FAULT
Figure 2. Fast Fault Timing
RESET
tWDI < tWD2 (max)
WDI WDPO
SLOW FAULT
Figure 3. Slow Fault Timing
tWD1 (max) < tWDI < tWD2 (min) RESET
WDI
H WDPO L NORMAL OPERATION (NO PULSING, OUTPUT STAYS HIGH)
Figure 4. Normal Operation, WDPO Not Asserted _______________________________________________________________________________________ 7
P Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323/MAX6324
VTH VCC 100ms (min) 100ms (min)
120ns (typ) RESET
20s (typ)
MR 1s (min)
Figure 5. RESET Timing Relationship
falls below the preset threshold or when the manual reset input (MR) is asserted. The RESET output remains asserted for at least 100ms after VCC has risen above the reset threshold and MR is deasserted (Figure 5). For noisy environments, bybass VCC with a 500pF (min) capacitor to ensure correct operation. The MAX6323 has a push-pull output stage, and the MAX6324 utilizes an open-drain output. Connect a pullup resistor on the RESET output of the MAX6324 to any supply up to +6V. Select a resistor value large enough to register a logic low (see Electrical Characteristics) and small enough to register a logic high while supplying all input leakage currents and leakage paths connected to the RESET line. A 10k pullup is sufficient in most applications.
Applications Information
Negative-Going VCC Transients
The MAX6323/MAX6324 are relatively immune to shortduration negative-going V CC transients (glitches), which usually do not require the entire system to shut down. Typically, 200ns large-amplitude pulses (from ground to VCC) on the supply will not cause a reset. Lower amplitude pulses result in greater immunity. Typically, a VCC transient that falls 100mV below the reset threshold and lasts less than 20s will not trigger a reset (see Typical Operating Characteristics). An optional 0.1F bypass capacitor mounted close to VCC provides additional transient immunity.
Manual Reset Input
Many P-based products require manual reset capability to allow an operator or external logic circuitry to initiate a reset. The manual reset input (MR) can connect directly to a switch without an external pullup resistor or debouncing network. MR is internally pulled up to VCC and, therefore, can be left unconnected if unused. MR is designed to reject fast, negative-going transients (typically 100ns pulses), and it must be held low for a minimum of 1s to assert the reset output (Figure 5). A 0.1F capacitor from MR to ground provides additional noise immunity. After MR transitions from low to high, reset will remain asserted for the duration of the reset timeout period, at least 100ms.
8
When VCC falls below +1.2V, the MAX6323 RESET output no longer sinks current; it becomes an open circuit. Therefore, high-impedance CMOS logic inputs connected to RESET can drift to undetermined voltages. This does not present a problem in most applications, since most Ps and other circuitry are inoperative with V CC below +1.2V. However, in applications where RESET must be valid down to 0, adding a pulldown resistor to RESET causes any stray leakage currents to flow to ground, holding RESET low (Figure 6). R1's value is not critical; 100k is large enough not to load RESET and small enough to pull RESET to ground. This scheme does not work with the open-drain output of the MAX6324.
Ensuring a Valid Reset Output Down to VCC = 0
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P Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323/MAX6324
VCC VCC
VCC
VCC
VCC P RESET RESET INPUT GND
MAX6323
RESET R1 100k
MAX6324
GND
GND
Figure 6. RESET Valid to VCC = Ground Circuit
Figure 7. Interfacing to Ps with Bidirectional Reset Pins
Interfacing to Ps with Bidirectional Reset Pins
Since the RESET output on the MAX6324 is open-drain, this device easily interfaces with Ps that have bidirectional reset pins, such as the Motorola 68HC11. Connecting the P supervisor's RESET output directly to the microcontroller's (C's) RESET pin with a single pullup resistor allows either device to assert reset (Figure 7).
MAX6324 Open-Drain RESET Output Allows Use with Multiple Supplies
Generally, the pullup resistor connected to the MAX6324 will connect to the supply voltage that is being monitored at the IC's VCC pin. However, some systems may use the open-drain output to level-shift from the monitored supply to reset circuitry powered by some other supply (Figure 8). Keep in mind that as the MAX6324's VCC decreases below +1.2V, so does the IC's ability to sink current at RESET. Also, with any pullup resistor, RESET will be pulled high as VCC decays toward 0. The voltage where this occurs depends on the pullup resistor value and the voltage to which it is connected.
technique avoids a "stuck" loop in which the watchdog time would continue to be reset within the loop, keeping the watchdog from timing out. Figure 9 shows an example of a flow diagram where the I/O driving the watchdog input is set high at the beginning of the program, set low at the beginning of every subroutine or loop, then set high again when the program returns to the beginning. If the program should "hang" in any subroutine, the problem would be quickly corrected, since the I/O is continually set low and the watchdog time is allowed to time out, causing a reset or interrupt to be issued.
WDPO to MR Loopback
An error detected by the watchdog often indicates that a problem has occurred in the P code execution. This could be a stalled instruction or a loop from which the processor cannot free itself. If the P will still respond to a nonmaskable input (NMI), the processor can be redirected to the proper code sequence by connecting the WDPO output to an NMI input. Internal RAM data should not be lost, but it may have been contaminated by the same error that caused the watchdog to time out. If the processor will not recognize NMI inputs, or if the internal data is considered potentially corrupted when a watchdog error occurs, the processor should be restarted with a reset function. To obtain proper reset timing characteristics, the WDPO output should be connected to the MR input, and the RESET output should
Watchdog Software Considerations
To help the watchdog timer monitor software execution more closely, set and reset the watchdog input at different points in the program, rather than "pulsing" the watchdog input high-low-high or low-high-low. This
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9
P Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323/MAX6324
+3.3V +5.0V
START
RPULLUP VCC VCC 5V SYSTEM
SET WDI LOW
MAX6324
RESET RESET INPUT GND
SUBROUTINE OR PROGRAM LOOP SET WDI HIGH
GND
RETURN
Figure 8. MAX6324 Open-Drain RESET Output Allows Use with Multiple Supplies
END
drive the P RESET input (Figure 10). The short 1ms WDPO pulse output will assert the manual reset input and force the RESET output to assert for the full reset timeout period (100ms min). All internal RAM data is lost during the reset period, but the processor is guaranteed to begin in the proper operating state.
Figure 9. Watchdog Flow Diagram
Standard Versions
MAX6323AUT29 MAX6323AUT46 MAX6323CUT29 MAX6323CUT46 MAX6323DUT29 MAX6323DUT46 MAX6323HUT29 MAX6323HUT46 MAX6324AUT29 MAX6324AUT46 MAX6324BUT29 MAX6324BUT46 MAX6324EUT29 MAX6324EUT46 MAX6324HUT29 MAX6324HUT46
Reset Threshold Range (-40C to +125C)
SUFFIX 46 44 31 29 26 23 MIN 4.50 4.25 3.00 2.85 2.55 2.25 TYP 4.63 4.38 3.08 2.93 2.63 2.32 MAX 4.75 4.50 3.15 3.00 2.70 2.38 UNITS
V
Chip Information
TRANSISTOR COUNT: 1371 PROCESS: BiCMOS
10
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P Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323/MAX6324
VCC 500pF VCC *RPULLUP VCC P RESET I/O
MAX6323 MAX6324
RESET MR GND WDI WDPO
*MAX6324 ONLY
Figure 10. WDPO to MR Loopback Circuit
Typical Operating Circuit
VCC 500pF VCC *RPULLUP VCC P RESET I/O NMI
MAX6323 MAX6324
RESET MR GND WDI WDPO
*MAX6324 ONLY
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11
P Supervisory Circuits with Windowed (Min/Max) Watchdog and Manual Reset MAX6323/MAX6324
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
6LSOT.EPS
MAX6323/MAX6324
PACKAGE OUTLINE, SOT-23, 6L
21-0058
F
1
1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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